Semiconductor device and power converter, driving inverter, general-purpose inverter and high-power high-frequency communication device using same

ABSTRACT

In a semiconductor device that uses a silicon carbide semiconductor substrate having p type, n type impurity semiconductor regions formed by ion implantation, the electrical characteristics of the end semiconductor device can be improved by decreasing the roughness of the silicon carbide semiconductor substrate surface. The semiconductor device of this invention is a Schottky barrier diode or a p-n type diode comprising at least one of a p type semiconductor region and n type semiconductor region selectively formed in a silicon carbide semiconductor region having an outermost surface layer surface that is a (000-1) surface or a surface inclined at an angle to the (000-1) surface, and a metal electrode formed on the outermost surface layer surface, that controls a direction in which electric current flows in a direction perpendicular to the outermost surface layer surface from application of a voltage to the metal electrode.

TECHNICAL FIELD

This invention relates to a semiconductor device formed on a siliconcarbide substrate having a prescribed substrate crystalline surfaceorientation, and to an electric power converter, drive inverter,general-purpose inverter and super-power high-frequency communicationequipment using the semiconductor device.

BACKGROUND ART

With respect to a semiconductor device using silicon carbide on theuppermost layer of a semiconductor substrate and to a method ofmanufacturing the same, as described in the following, there have been anumber of publications and disclosures of inventions, but in the priorart, a semiconductor device using a silicon carbide substrate has astructure in which a gate electrode is normally formed on the (0001)face. In this case, when forming a p type or n type region by ionimplantation in the (0001) face, ion implantation of a p type or n typeimpurity is followed by heat treatment at a high temperature of 1500° C.or above for activation, so silicon evaporates from the silicon carbidesurface, leading to increased roughness of the silicon carbide surface.This results in reduced channel mobility of metal-insulationfilm-semiconductor field-effect transistors (MISFETs) ormetal-semiconductor field-effect transistors (MESFETs), and increasedleak current in Schottky barrier diodes (SBDs) and junction typefield-effect transistors (JFETs) caused by larger crystal defects in theion implantation region, problems which make practical use impossible.

For example, Non-Patent Document 1 describes the occurrence of steppunching due to high-temperature heat treatment for impurity activation,producing increased surface roughness, so that in order to reduce theOn-resistance value of a 4H—SiC power MOSFET to the theoretical value,the channel mobility was no more than 1 cm²/Vs, even though 100 cm²/Vsor more is needed.

[Non-Patent Document 1]: J. A. Cooper, Jr., M. R. Melloch, R. Singh, A.Agarawal, J. W. Palmour, IEEE Transaction on electron devices, vol. 49,No, 4, Apr. 2002, p. 658

Also, Non-Patent Document 2 describes a DiMOSFET type SiC power MOSFETin which channel mobility at room temperature was only 22 cm²/Vs, due tothe use of heat treatment in the region of 1600° C. following ionimplantation of a p type impurity (aluminum).

[Non-Patent Document 2]: S. H. Ryu, A. Agarwal, J. Richmond, J. Palmour,N. Saks and J. Williams, IEEE Electron device letters, vol. 23, No. 6,Jun. 2002, p. 321

Also, Non-Patent Document 3 describes a lateral DMOSFET type SiC powerMOSFET in which channel mobility was only 4 to 5 cm²/Vs, due to the useof activation heat treatment at 1600° C. for 40 minutes following ionimplantation of a p type impurity (aluminum).

[Non-Patent Document 3]: J. Spitz, M. R. Melloch, J. A. Cooper, Jr., M.A Capano, IEEE Electron device letters, vol. 19, No. 4, April 1998, p.100

DISCLOSURE OF THE INVENTION

Thus, in each of the above prior-art references, a semiconductor devicehaving a p type or n type region formed on a silicon carbide substrateby impurity ion implantation, is formed on the (0001) face. However, asilicon carbide substrate has various surface orientations, and bycontriving the surface orientation and the impurity heat treatmentmethod in that surface orientation, it is possible to suppress theroughness on the silicon carbide substrate surface following theimpurity activation heat treatment, improving the electricalcharacteristics of the semiconductor device.

Non-Patent Document 4 reports the operation of a MOSFET formed usingchannel doping by implanting an impurity below the gate oxide film on a6H—SiC (000-1) surface, but only an n type semiconductor region wasformed by ion implantation, the gate oxide film being formed by dryoxidation, so the structure differs from that of the semiconductordevice described below in the, examples.

[Non-Patent Document 4]: S. Ogino, T. Oikawa, K. Ueno, Mat. Sci. Forum,338-342 (2000), p. 1101

This invention is proposed in view of the above, and has as its object,in a semiconductor device that uses a silicon carbide substrate having ptype, n type semiconductor impurity regions formed by ion implantation,to improve the ultimate electrical characteristics of the semiconductordevice by reducing surface roughness of the silicon carbide substrate.

In accordance with this invention, the above object is attained by asemiconductor device characterized in that at least an outermost surfacelayer has a semiconductor region constituted by (000-1) surface siliconcarbide, and at least one of a p type semiconductor region and an n typesemiconductor region is selectively formed in the silicon carbidesemiconductor region by ion implantation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional schematic diagram of a Schottky barrierdiode that is an example of the semiconductor device of the presentinvention.

FIG. 2 is a cross-sectional schematic diagram of a semiconductor devicehaving a lateral type structure (lateral resurf MOS structure) that isan example of a lateral MIS field-effect transistor according to thepresent invention.

FIG. 3 is a cross-sectional schematic diagram of a semiconductor devicehaving a lateral type structure (lateral resurf MOS structure) thatdiffers from the structure of FIG. 2, which is an example of a lateraltype MIS field-effect transistor according to the present invention.

FIG. 4 is a cross-sectional schematic diagram of a vertical type MISfield-effect transistor that is an example of the semiconductor deviceof the present invention.

FIG. 5 is a diagram that shows the measured results of surfaceroughness) (RMS) versus length of heat treatment of the (0001) face and(000-1) surface of silicon carbide substrates.

FIG. 6 is a circuit diagram of a motor drive power IC that uses thevertical type MIS field-effect transistor and Schottky barrier diode ofthe present invention.

FIG. 7 is a diagram showing the hydrogen density distribution in a gateinsulation film, measured using a SIMS (secondary ion massspectrometer).

BEST MODE FOR CARRYING OUT THE INVENTION

A method of manufacturing a Schottky barrier diode, a lateral type MISfield-effect transistor and a vertical type MIS field-effect transistorthat are examples of a semiconductor device formed using the (000-1)surface of a silicon carbide substrate will be described. This will befollowed by showing the results of measurements, by an atomic forcemicroscope, of the surface roughness of substrates that have beenheat-treated following ion implantation in the (0001) face used in asemiconductor device that uses a normal silicon carbide semiconductorsubstrate and in the (000-1) surface proposed by the present invention.

FIG. 1 is a cross-sectional schematic diagram of a Schottky barrierdiode that is an example of the semiconductor device of the presentinvention.

This Schottky barrier diode was manufactured by the following procedure.First, the chemical vapor method was used to grow a 10 μm n typeepitaxial layer 2 having a nitrogen impurity concentration of 1×10¹⁶cm⁻³ on the (000-1) surface of an n type 4H—SiC bulk substrate 1(resistivity: 0.002 Ωcm, thickness: 300 μm). The bulk substrate 1 andepitaxial layer 2 form a silicon carbide semiconductor region, and theoutermost surface layer of the epitaxial layer 2 has a (000-1) surface.

In order to form a guard ring around a Schottky electrode 6, 1×10¹⁷ ionsper cm³ of a p type impurity constituted by aluminum or boron wereimplanted into the region forming the guard ring of the epitaxial layer2, forming the guard ring p type impurity region (p type semiconductorregion) 3. A silicon dioxide film formed by the low-pressure chemicalvapor method was used as the mask for this ion implantation. After usinghydrofluoric acid to form the openings for the ion implantation in thesilicon dioxide film, ion implantation is carried out at a temperatureranging from room temperature to 1000° C.; in this embodiment the ionswere implanted at room temperature.

Next, the temperature is elevated from 1200° C. or below to from 1500°C. to 2000° C., preferably to 1700° C., within 1 minute, in an argonatmosphere, to carry out activation heat treatment for a period of from10 seconds to 10 minutes. In this embodiment, heat treatment was carriedout at 1500° C. for 5 minutes. Following this, the sputtering method orvapor deposition method is used to form an Ni layer or a Ti layer(backside electrode 4) on the backside (0001) face of the bulk substrate1, after which heat treatment at around 1000° C. in an inert atmosphereis carried out, forming the backside electrode 4. Next, a passivationoxide film 5 is grown on the ion-implanted side of the epitaxial layer2, portions are opened for forming the Schottky electrode, and thesputtering or vapor deposition method is used to form an Ni or TiSchottky electrode (metal electrode) 6. To complete the device, a metalwire 7 of aluminum alloy is formed by the sputtering or vapor depositionmethod. This semiconductor device has a gate (Schottky electrode) on the(000-1) surface of the silicon carbide semiconductor region and a drain(backside electrode) on the (0001) face, and by applying a voltage tothe gate functioned as a rectifying device that controls the flow ofcurrent in the direction of the C axis perpendicular to the (000-1)plane.

In the manufacture of the Schottky barrier diode, the p typesemiconductor region 3 is formed by ion implantation in the siliconcarbide semiconductor regions 1 and 2 having (000-1) outermost surfacelayers, so surface roughness of the silicon carbide semiconductorsubstrate 1 and 2 can be reduced, thereby improving the On-resistance,blocking voltage and other such electrical characteristics of theSchottky barrier diode.

Also, impurity activation heat treatment is implemented after the p typesemiconductor region 3 is formed by ion implantation, enabling furtherimprovement of the roughness of the outermost surface layers of thesilicon carbide semiconductor regions 1 and 2, thereby enabling acorresponding further improvement in the electrical characteristics ofthe Schottky barrier diode.

Although the above explanation was made with reference to the presentinvention applied to a Schottky barrier diode that controls the flow ofcurrent in the direction of the C axis perpendicular to the (000-1)plane, it may also be applied to a p-n type diode that similarlycontrols the flow of current in the direction of the C axisperpendicular to the (000-1) plane.

FIG. 2 is a cross-sectional schematic diagram of a semiconductor devicehaving a lateral type structure (lateral resurf MOS structure) that isan example of a lateral MIS field-effect transistor according to thepresent invention. First, the chemical vapor method was used to grow a10˜15 μm p type epitaxial layer 12, with aluminum as the impurity, onthe (000-1) surface of a p type 4H—SiC bulk substrate 11 (resistivity: 2Ωcm, thickness: 300 μm). The p type impurity concentration was 5×10¹⁵cm⁻³. The SiC bulk substrate 11 may be n type. The bulk substrate 11 andepitaxial layer 12 form a silicon carbide semiconductor region, and theoutermost surface layer of the epitaxial layer 12 has a (000-1) surface.

Next, in order to form a source region and a drain region, an ionimplantation mask is formed using a thermal oxidation film or an SiO₂film formed by CVD (Chemical Vapor Deposition). In this embodiment, anLTO (Low Temperature Oxide) film is used for the ion implantation mask.The LTO film is formed by reacting silane and oxygen at from 400° C., to800° C. to deposit silicon dioxide.

Following this, photolithography is used to form the source region andthe drain region, after which HF (hydrofluoric acid) is used to etchopenings in the LTO film for the source region and drain region intowhich ions are implanted, and the openings arc used to implant ions ofnitrogen, phosphorus or arsenic at 500° C., forming n type impurityregions used to constitute a source 131 and a drain 132.

Then, the same method as in the case of the source 131 and drain 132 isused to perform ion implantation, thereby forming an n⁻ impurity region14 for high blocking voltage. This region can be divided into two ormore regions in which the concentration increases going from the gatetowards the drain. As in the case of the source 131, the drain 132 andthe n impurity region 14, to establish ohmic contact with the p typeepitaxial layer 12, an ion implantation mask is formed and aluminum orboron ions are implanted to form a p⁺ impurity region 15. Here the “⁻”of n⁻ indicates a lower concentration than the n type impurityconcentration of the n type region, and the “⁺” of p⁺ indicates a higherconcentration than the p type impurity concentration of the p typeregion.

Next comes impurity activation heat treatment for a period of from 10seconds to 10 minutes in an argon atmosphere at a temperature range offrom 1500° C. to 2000° C., followed by cooling to or below a temperatureof 1200° C. for 1 to 5 minutes. In this embodiment, heat treatment wascarried out at 1500° C. for 5 minutes. It is more preferable for thetemperature to be elevated from 1200° C. or below to the heat treatmenttemperature within 1 minute.

Following this, a passivation SiO₂ film 16 is formed on the epitaxiallayer 12 as a thermal oxidation film or LTO film. In this embodiment, itis formed as an LTO film. An opening is made for the gate insulationfilm portion, and a gate insulation film 17 that is approximately 50 nmis formed by oxidation at 800° C.˜1200° C. using O₂ gas or O₂ gascontaining H₂O (water), All of the gate insulation film 17 or at leastthe layer in contact with the epitaxial layer 12 is formed by thermaloxidation of silicon carbide. When thermal oxidation in an O₂ atmospherecontaining water is used, the gate insulation film that is formedcontains hydrogen. A gate electrode (Metal electrode) 18 is formed onthe gate insulation film 17. The gate electrode 18 can be formed usingaluminum or n type or p type polysilicon. The gate insulation film 17and the gate electrode 18 are called gates. Next, contact holes areetched in the SiO₂ film 16 on the source 131 and drain 132. Then, afterusing vapor deposition or the sputtering method to form a metalcontaining nickel, titanium or aluminum, or a layered film of these, RIEor wet etching is used to form a contact electrode (metal electrode) 19which is ohmic-contacted using heat treatment at about 1000° C. in aninert atmosphere. To complete the device, a metal containing aluminum isformed by vapor deposition or the sputtering method, which is followedby the forming of a metal wire 10, using RIE or wet etching.

FIG. 3 is a cross-sectional schematic diagram of a lateral typesemiconductor device having a lateral resurf MOS structure that differsfrom the structure of FIG. 2, which is an example of a lateral MSfield-effect transistor according to the present invention. Whilebasically the same as in FIG. 2, it differs from that of FIG. 2 in thatthe epitaxial layer 12 is provided with a p type impurity region 122,and the above source 131 and p⁺ impurity region 15 are formed in theepitaxial layer 122.

The lateral resurf MOSFET semiconductor devices shown in FIGS. 2 and 3have a gate (comprised of a gate insulation film and gate electrode),source and drain on the (000-1) surface of the silicon carbidesemiconductor region, and when a voltage is applied to the gate, theyare switching devices that control the flow/interception of electriccurrent flowing in the (000-1) plane.

A MES type field-effect transistor is another example of a lateralresurf semiconductor: device. This is the same as a lateral resurfMOSFET semiconductor device in that it has a gate, source and drain onthe (000-1) surface and when a voltage is applied to the gate, itcontrols the flow/interception of electric current flowing in the(000-1) plane. However, it does not have a gate insulation film belowthe gate electrode, but instead has a gate electrode of metal that isformed directly on the silicon carbide semiconductor.

In the manufacture of the lateral type semiconductor device, the source131, drain 132, n⁻ impurity region 14, p⁺ impurity region 15 and othersuch p type and n type semiconductor regions are formed by ionimplantation in the silicon carbide semiconductor regions 11 and 12having (000-1) outermost surface layers, so surface roughness of thesilicon carbide semiconductor substrate 11 and 12 can be reducedcompared with the (0001) face, thereby improving the On-resistance,blocking voltage and other such electrical characteristics of thelateral type semiconductor device.

After forming the p type and n type semiconductor regions, such as thesource 131, drain 132, n⁻ impurity region 14, p⁺ impurity region 15 andso forth, by ion implantation, the temperature is elevated from 1500° C.to 2000° C. in an inert atmosphere to carry out impurity activation heattreatment for a period of from 10 seconds to 10 minutes, and, moreover,the temperature is elevated from 1200° C. or below to from 1500° C. to2000° C. in an inert atmosphere, within 1 minute, to carry out impurityactivation heat treatment at that temperature for a period of from 10seconds to 10 minutes, enabling further improvement of the roughness ofthe outermost surface layers of the silicon carbide semiconductorregions 11 and 12, thereby enabling a corresponding further improvementin the electrical characteristics of the lateral type semiconductordevice.

FIG. 4 is a cross-sectional schematic diagram of a vertical type MISfield-effect transistor that is an example of the semiconductor deviceof the present invention. In the semiconductor device of this invention,a bulk substrate 21 is constituted as a high concentration n type 4H—SiCsubstrate on the (000-1) surface of which an epitaxial layer 22 of lowconcentration n type silicon carbide is formed. The bulk substrate 21and epitaxial layer 22 form a silicon carbide semiconductor region, andthe outermost surface layer of the epitaxial layer 22 has a (000-1)surface.

Next, a first n type impurity region 23 constituted by silicon carbidehaving a first concentration is grown epitaxially on the epitaxial layer22 by the chemical vapor method. Then, after the silicon carbidesubstrate has been cleaned using standard RCA cleaning, RIE (reactiveion etching) is used to form lithography alignment marks.

Then, a LTO (low temperature oxide) film is used for an ion implantationmask. The LTO film is formed by reacting silane and oxygen at from 400°C. to 800° C. to deposit silicon dioxide on the silicon carbidesubstrate (first n type impurity region 23). Next, after forming theregion by ion implantation, using lithography, BY (hydrofluoric acid) isused to open the LTO film by etching. Then, first p type silicon carbideregions (p type (p⁻) wells) 24, 24 are formed adjoining both sides ofthe first n type impurity region 3 by implanting aluminum or boron ionsinto the first n type impurity region 23.

In addition, for high blocking voltage, ion implantation is used toform, in the lower region of the first p type silicon carbide region 24,a second p type silicon carbide region (p⁺ region) 24 a having a higherconcentration than the first p type silicon carbide region 24. Thesecond p type silicon carbide region 24 a is formed by the implantationof 10¹⁸ to 10¹⁹ ions of aluminum or boron per cm⁻³, ensuring improvedblocking voltage.

If required, a buried channel region 25 constituting an n type impurityregion having a sufficient impurity concentration can be selectivelyformed inwards from the surface of the first p type silicon carbideregion 24, below the region where the gate oxide film is going to beformed. This buried channel region 25 is formed at a depth (Lbc)=0.3 μmby the implantation of 1×10¹⁵˜5×10¹⁷ ions per cm³, Multiple implantationsteps were used to achieve a total phosphorus dosage amount of 7×10¹⁵cm⁻², and the implantation energy was controlled within the range 40keV˜250 keV to achieve formation having the desired depth.

Next, at a location away from the first n type impurity region 23,second n type impurity regions (n⁺ sources) 26, 26 are selectivelyformed inwards from the surface of the first p type silicon carbideregions 24, 24.

Also if necessary, using ion implantation, a third n type impurityregion 27 having a third concentration can be selectively formed inwardsfrom the surface of the first p type silicon carbide region 24, betweenthe second n type impurity region 26 and the buried channel region 25.

Next comes impurity activation heat treatment for a period of from 10seconds to 10 minutes in an argon atmosphere in a temperature range offrom 1500° C. to 2000° C., followed by cooling to or below a temperatureof 1200° C. for 1 to 5 minutes. In this embodiment, heat treatment wascarried out at 1500° C. for 5 minutes. It is more preferable for thetemperature to be elevated from 1200° C. or below to the heat treatmenttemperature within 1 minute.

This is followed by oxidation at 1200° C. in an O₂ atmosphere of or O₂atmosphere containing H₂O to form approximately 50 nm gate oxide films28, 28. All of the gate insulation film 28 or at least the layer incontact with the epitaxial layer 22 is formed by thermal oxidation ofsilicon carbide. When thermal oxidation in an O₂ atmosphere containingwater is used, the gate insulation film that is formed containshydrogen. FIG. 7 is a diagram showing the hydrogen density distributionin the gate insulation film, measured using a SIMS (secondary ion massspectrometer). With the hydrogen distribution centering on the interfacebetween the silicon carbide substrate (000-1) surface and the gateinsulation film, if the hydrogen content is not less than 1×10¹⁹ cm⁻³and not more than 1×10²² cm⁻³, interface defects are reduced, improvingchannel mobility. Next came 30 minutes of annealing in argon, followedby cooling to room temperature in the argon. Then, gate electrodes 29,29 were formed. The gate electrodes 29, 29 were formed of p⁺polysilicon. Methods of forming the gate electrodes 29, 29 from papolysilicon include; 1) after forming polycrystalline silicon by the CVDmethod, p type polycrystalline silicon is formed by ion implantation ofboron or boron fluoride, 2) after forming polycrystalline silicon by theCVD method, a SiO₂ film containing boron is formed by the CVD method orby spin-coating and diffused by heat treatment at 800° C. to 1100° C. toimplant the boron and form p type polycrystalline silicon, and 3)flowing silane and diborane together and heat treating at 600° C. toform polycrystalline silicon that is implanted with boron to form p typepolycrystalline silicon. In this embodiment, method 2) was used. Then,etching is used to complete the forming of the gate electrodes 29, 29.

Although in the above description, the gate electrode 29 was formed ofp⁺ polysilicon, it may be formed of aluminum, aluminum alloy ormolybdenum metal. When the gate electrode 29 is formed of aluminum,aluminum alloy or molybdenum metal, the interface with the gate oxidefilm 28 is better than the interface with the gate oxide film 28 whenpolysilicon is used for the gate electrode 29, and it was confirmed thatit had the effect of raising the channel mobility.

A silicide film 30 of WSi₂, MoSi₂ or TiSi₂ may be formed on the abovegate electrodes 29, 29.

After then using the CVD method to form an interlayer insulation film 31by deposition, contact holes are etched in the interlayer insulationfilm 31 over the second n type impurity regions (n⁺ sources) 26, 26 andthe first p type silicon carbide regions (p⁻ wells) 24, 24. Then, afterusing vapor deposition or the sputtering method to form a metalcontaining nickel, titanium or aluminum, or a layered film of an alloyof these, RIE or wet etching is used to form a metal wire 32 ofpolycrystalline silicon, short-circuiting the first p type siliconcarbide regions 24 and the second n type impurity regions 26. In thisembodiment, the metal wire 32 is formed by evaporation of aluminumfollowed by wet etching.

Next, drain electrode 33 is formed on the backside of the bulk substrate21 by vapor deposition or sputtering a metal to the required thickness.In this embodiment, this was done by the sputtering of nickel. Ifnecessary, heat treatment can be carried out in an argon atmosphere at1000° C. for 5 minutes, thereby completing the vertical type AUSfield-effect transistor.

With respect to vertical type semiconductor devices, there is also ajunction type field-effect transistor. This has a structure in whichthere is no oxide film below the gate electrode; instead, the metal gateelectrode is formed directly on the silicon carbide. Theflow/interception of electric current flowing in a directionperpendicular to the (000-1) plane is controlled by applying a voltageto the gate electrode.

In the manufacture of the vertical type MIS field-effect transistor andjunction type field-effect transistor, first n type silicon carbideregion 23, first p type silicon carbide region 24, second p type siliconcarbide region 24 a and other such p type and n type semiconductorregions are formed by ion implantation in the silicon carbidesemiconductor substrates (silicon carbide semiconductor regions) 21 and22 having (000-1) outermost surface layers, so surface roughness can bereduced compared with the (0001) face of the silicon carbidesemiconductor substrates 21 and 22, thereby improving the On-resistance,blocking voltage and other such electrical characteristics of thevertical type MIS field-effect transistor and junction type field-effecttransistor.

After forming the first n type silicon carbide region 23, first p typesilicon carbide region 24, second p type silicon carbide region 24 a andother such p type and n type semiconductor regions by ion implantation,impurity activation heat treatment is carried out, enabling furtherimprovement of the roughness of the outermost surface layers of thesilicon carbide semiconductor regions 21 and 22, thereby enabling acorresponding further improvement in the electrical characteristics ofthe vertical type MIS field-effect transistor and junction typefield-effect transistor.

By improving the electrical characteristics of the above-describedsemiconductor device according to the present invention, such as, forexample, Schottky barrier diode, p-n type diode, junction typefield-effect transistor, lateral type MIS field-effect transistor andvertical type MIS field-effect transistor, electric power converters,drive inverters, general-purpose inverters and MES type field-effecttransistors can be incorporated as components of GHz-band super-powerhigh-frequency communication equipment, thereby helping to improve theperformance of such apparatuses. FIG. 6 is a circuit diagram of a motordrive power IC. The inverter portion (A) of this power IC circuit usesthe vertical type MIS field-effect transistor and Schottky barrier diodeof the present invention.

Moreover, although in the above description the outermost surface layerof the silicon carbide semiconductor region has a (000-1) surface andthat surface is subjected to various treatments, the outermost surfacelayer surface may have a surface plane that is inclined at an angle tothe (000-1) surface (for example, within 10 degrees, and preferably byabout 3.5 degrees), and that surface may be subjected to varioustreatments.

Next, the effect of heat treatment time on the surface roughness (RMS)of the (0001) face and (000-1) surface of silicon carbide semiconductorsubstrates will be explained.

In order to examine the effect that activation heat treatment has onsurface roughness, (0001) face silicon carbide semiconductor substratesand (000-1) surface silicon carbide semiconductor substrates were heatedfrom room temperature to 1600° C. in 1 minute and subjected toactivation heat treatment for 1 minute and 10 minutes, and an atomicforce microscope was used to observe the surfaces and measure thesurface roughness (RMS). The results are shown in FIG. 5. As can be seenfrom FIG. 5, whether at a heat treatment time of 1 minute or 10 minutes,the (000-1) surface had less surface roughness (RMS) than the (0001)face, about half as much.

Therefore, by forming a semiconductor device having ion implantationregions in the (000-1) surface, and forming a gate insulation film orgate electrode thereon and fabricating a lateral type MIS field-effecttransistor, vertical type MIS field-effect transistor, MES typefield-effect transistor, junction type field-effect transistors andother such semiconductor devices, when the device is on, there is lessscattering of flowing electrons caused by silicon carbide substratesurface roughness, facilitating the flow of electrons and lowering theOn-resistance. Also, the high frequency characteristics of MES typefield-effect transistors are improved. Moreover, when forming thejunction portions of lateral type MIS field-effect transistors, verticaltype WIS field-effect transistors, UES type field-effect transistors,junction type field-effect transistors, Schottky barrier diodes and p-ntype diodes, it is harder for crystal defects to form, so when a reverse(negative) voltage is applied to the gate electrode, leak current isreduced, while at the same time blocking voltage can be improved.

INDUSTRIAL APPLICABILITY

As described in the foregoing, the semiconductor device of thisinvention has a silicon carbide semiconductor region in which at leastthe outermost surface layer has a (000-1) surface, and in this siliconcarbide semiconductor region, at least one selected from a p typesemiconductor region and an n type semiconductor region is selectivelyformed by ion implantation, enabling roughness of the silicon carbidesemiconductor region surface to be reduced, thereby making it possibleto improve electrical characteristics of the semiconductor device, suchas the On-resistance and the blocking voltage.

Also, after the p type semiconductor region or n type semiconductorregion is formed by ion implantation, impurity activation heat treatmentis implemented, thereby enabling further reduction in the roughness ofthe outermost surface layer of the silicon carbide semiconductor region,and a corresponding further improvement in the electricalcharacteristics of the semiconductor device.

1. A semiconductor device that is a Schottky barrier diode or p-n typediode comprising at least one of a p type semiconductor region and ntype semiconductor region selectively formed in a silicon carbidesemiconductor region having an outermost surface layer surface that is a(000-1) surface or a surface inclined at an angle to the (000-1)surface, and a metal electrode formed on the outermost surface layersurface, that controls a direction in which electric current flows in adirection perpendicular to the outermost surface layer surface fromapplication of a voltage to the metal electrode.
 2. The semiconductordevice according to claim 1, wherein the silicon carbide semiconductorregion is p type or n type.
 3. The semiconductor device according toclaim 1, wherein formation of the p type semiconductor region or n typesemiconductor region by implantation of impurity ions in the siliconcarbide semiconductor region is followed by implementation of impurityactivation heat treatment for a period of 10 seconds to 10 minutes at atemperature of from 1500° C. to 2000° C. in an inert atmosphere.
 4. Thesemiconductor device according to claim 1, wherein formation of the ptype semiconductor region or n type semiconductor region by implantationof impurity ions in the silicon carbide semiconductor region is followedby elevation of a temperature from 1200° C. or below to from 1500° C. to2000° C. within 1 minute, in an inert atmosphere, and implementation ofimpurity activation heat treatment for a period of 10 seconds to 10minutes at that temperature.
 5. The semiconductor device according toclaim 1, wherein the silicon carbide semiconductor region on a substrateside is 4H—SiC.
 6. An electric power converter constituted using thesemiconductor device according to claim
 1. 7. A drive inverterconstituted using the semiconductor device according to claim
 1. 8. Ageneral-purpose inverter constituted using the semiconductor deviceaccording to claim
 1. 9. A semiconductor device that is a MES typefield-effect transistor or junction type field-effect transistorcomprising at least one of a p type semiconductor region and n typesemiconductor region selectively formed in a silicon carbidesemiconductor region having an outermost surface layer surface that isa: (000-1) surface or a surface inclined at an angle to the (000-1)surface, and a metal electrode formed on the outermost surface layersurface, that, when a voltage is applied to the metal electrode,functions as a switching device that controls electric currentflow/interception.
 10. A super-power high-frequency communicationapparatus constituted using the MES type field-effect transistoraccording to claim
 9. 11. The semiconductor device according to claim 9,wherein the silicon carbide semiconductor region is p type or n type.12. The semiconductor device according to claim 9, wherein formation ofthe p type semiconductor region or n type semiconductor region byimplantation of impurity ions in the silicon carbide semiconductorregion is followed by implementation of impurity activation heattreatment for a period of 10 seconds to 10 minutes at a temperature offrom 1500° C. to 2000° C. in an inert atmosphere.
 13. The semiconductordevice according to claim 9, wherein formation of the p typesemiconductor region or n type semiconductor region by implantation ofimpurity ions in the silicon carbide semiconductor region is followed byelevation of a temperature from 1200° C. or below to from 1500° C. to2000° C. within 1 minute, in an inert atmosphere, and implementation ofimpurity activation heat treatment for a period of 10 seconds to 10minutes at that temperature.
 14. The semiconductor device according toclaim 9, wherein the silicon carbide semiconductor region on a substrateside is 4H—SiC.
 15. An electric power converter constituted using thesemiconductor device according to claim
 9. 16. A drive inverterconstituted using the semiconductor device according to claim
 9. 17. Ageneral-purpose inverter constituted using the semiconductor deviceaccording to claim
 9. 18. A semiconductor device comprising at least oneof a p type semiconductor region and n type semiconductor regionselectively formed in a silicon carbide semiconductor region having anoutermost surface layer surface that is a (000-1) surface or a surfaceinclined at an angle to the (000-1) surface, and a gate insulation filmformed on the (000-1) surface, wherein the gate insulation film containshydrogen.
 19. A semiconductor device characterized in comprising atleast one of a p type semiconductor region and n type semiconductorregion selectively formed in; a silicon carbide semiconductor regionhaving an outermost surface layer surface that is a (000-1) surface or asurface inclined at an angle to the (000-1) surface, and a gateinsulation film formed on the (000-1) surface, wherein the gateinsulation film contain not less than 1×10¹⁹ cm⁻³ and not more than1×10²² cm⁻³ hydrogen.
 20. A semiconductor device comprising at least oneof a p type semiconductor region and n type semiconductor regionselectively formed in a silicon carbide semiconductor region having anoutermost surface layer surface that is a (000-1) surface or a surfaceinclined at an angle to the (000-1) surface, and a gate insulation filmformed on the (000-1) surface, wherein the gate insulation film has alayer in contact with a silicon carbide substrate formed by thermaloxidation of silicon carbide in an atmosphere containing water and theformed gate insulation film contains not less than 1×10¹⁹ cm⁻³ and notmore than 1×10²² cm⁻³ hydrogen.
 21. A semiconductor device comprising atleast one of a p type semiconductor region and n type semiconductorregion selectively formed in a silicon carbide semiconductor regionhaving an outermost surface layer surface that is a (000-1) surface or asurface inclined at an angle to the (000-1) surface, and a gateinsulation film formed on the (000-1) surface, wherein the gateinsulation Mm contains nitrogen.
 22. The semiconductor device accordingto claim 21 that is a lateral MIS field-effect transistor having a gateinsulation film, gate electrode, source and drain on the outermostsurface layer surface of the silicon carbide semiconductor region that,when a voltage is applied to the gate electrode, functions as aswitching device that controls electric current flow/interception in theoutermost surface layer surface.
 23. The semiconductor device accordingto claim 21 that is a vertical type MIS field-effect transistor having agate insulation film, gate electrode and source on the outermost surfacelayer surface of the silicon carbide semiconductor region that, when avoltage is applied to the gate electrode, functions as a switchingdevice that controls flow/interception of electric current flowing inthe direction of the C axis perpendicular to the outermost surface layersurface.
 24. The semiconductor device according to claim 21, wherein thesilicon carbide semiconductor region is p type or n type.
 25. Thesemiconductor device according to claim 18, wherein formation of the ptype semiconductor region or n type semiconductor region by implantationof impurity ions in the silicon carbide semiconductor region is followedby implementation of impurity activation heat treatment for a period of10 seconds to 10 minutes at a temperature of from 1500° C. to 2000° C.in an inert atmosphere.
 26. The semiconductor device according to claim21, wherein formation of the p type semiconductor region or n typesemiconductor region by implantation of impurity ions in the siliconcarbide semiconductor region is followed by elevation of a temperaturefrom 1200° C. or below to from 1500° C. to 2000° C. within 1 minute, inan inert atmosphere, and implementation of impurity activation heattreatment for a period of 10 seconds to 10 minutes at that temperature.27. The semiconductor device according to claim 21, wherein the siliconcarbide semiconductor region on a substrate side is 4H—SiC.
 28. Anelectric power converter constituted using the semiconductor deviceaccording to claim
 21. 29. A drive inverter constituted using thesemiconductor device according to claim
 21. 30. A general-purposeinverter constituted using the semiconductor device according to claim21.